Xsight Labs announced on October 8, 2026, the E1L, the newest member of its E-Series data processing unit (DPU) portfolio.

The Arm-based device brings fully programmable DPU capability at up to 200G to power envelopes as low as 25 watts TDP, 15 watts typical in its eight-core, 100G configuration, and is aimed at edge, embedded, and other power-constrained infrastructure. The chip is scheduled to begin sampling in the second quarter of 2027.

One software stack from edge to core

The E1L shares its architecture and software with the company's 800G E1 DPU, and the company states the two are fully cross-platform compatible, so software written for one runs on the other.

According to the announcement, operators who wanted to bring DPU offload into a power-constrained site previously faced a choice between a proprietary software stack sized for a single chip or leaving offload out entirely.

The E1L is positioned as resolving that trade-off: full DPU offload from 25 watts on standard Linux tools, with no proprietary licensing.

Alongside the 800G E1, which draws under 75 watts, the E1L completes an E-Series line that runs a single software stack from 100G at the edge to 800G in the core.

"The E-Series now scales from 100 gigabits at the edge to 800 gigabits in the core on a unified architecture and software stack. Operators told us they needed DPU capability within the power envelopes they already rely on. The E1L delivers that," said Yossi Meyouhas, CEO of Xsight Labs.

Targeting the agentic AI workload

Xsight Labs framed the product in the context of AI shifting from models that answer questions to agents that take action.

The company argues that every agent query, lookup, and tool call becomes traffic to databases, storage, and the network, and that this infrastructure work lands on the same host CPUs intended for the AI workload itself. Agents touching critical systems also raise the bar for isolation, according to the announcement.

The E1L is designed to take that infrastructure work off the host, fully or in part, and run it in a separate, isolated domain, at a power envelope suited to sites outside the data center.

What a DPU does differently

Unlike a conventional network interface card, which only moves data, a DPU also carries its own processors and memory and runs infrastructure software itself, offloading networking, security, and storage tasks from the main server CPU.

Xsight Labs positions the E1L as a fully programmable, merchant-silicon alternative to proprietary DPUs, built on open standards and accelerating software-defined infrastructure without proprietary architectures or licensing requirements.

Low-power engineering

The E1L is engineered for space- and power-constrained environments and embedded applications where specialized data center cooling is limited or absent. It delivers fully programmable DPU capability at up to 200 Gbps, with TDP options from 25 W to 40 W and a typical draw of 15 to 25 W.

The power figures start with the silicon: the E1L is built on TSMC's N5 process, the same node as the E1, allowing it to do the same work in a smaller form factor with less energy and less heat.

The device is built on Arm Neoverse CSS N2 and designed for Arm SystemReady compatibility, running standard Linux and familiar frameworks including XDP, DPDK, and SPDK. This lets infrastructure teams develop and deploy programmable networking, storage, and security services without a proprietary software environment.

Eddie Ramirez, Vice President of Go-To-Market, Cloud AI at Arm, said, "AI infrastructure is expanding across a broader range of environments, making performance per watt and software flexibility critical for deployment. By building on Arm Neoverse CSS N2, Xsight Labs is bringing programmable, efficient compute from the edge to the data center while giving developers the benefits of a common software ecosystem."

Key specifications

The E1L offers 8, 16, or 22 Arm Neoverse N2 compute cores, with networking at up to 200 Gbps over 4 SerDes lanes. Memory support comprises up to 2 DDR5-5200 interfaces with inline encryption. On the security front, the chip provides line-rate AES-GCM for IPsec offload. The host interface consists of 20 PCIe Gen5 lanes across 6 dual-mode controllers with SR-IOV support.

Power is configurable at 25 W, 30 W, and 40 W TDP, with typical draws of 15 W, 18 W, and 25 W respectively. The software stack supports off-the-shelf Linux distributions along with XDP, DPDK, and SPDK integration.

The E1L is offered in three form factors, a discrete device, a COM Express module, and a 1RU server, all sharing the same software and feature set.

Availability

Sampling is scheduled to begin in the second quarter of 2027. Xsight Labs, an OCP Bronze member, will present the E1L at the 2026 Open Compute Project Global Summit, running October 12 to 15 in San Jose.

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