NVIDIA and TSMC have announced a broad expansion of their long-standing technology partnership, with the Taiwanese semiconductor giant now deploying NVIDIA accelerated computing and artificial intelligence tools across multiple stages of semiconductor design and manufacturing.

The collaboration, announced at NVIDIA GTC Taipei, encompasses computational lithography, transistor simulation, process control, defect inspection, and a new virtual fab environment built on NVIDIA Omniverse.

A Three-Decade Partnership Enters the Fab Floor

NVIDIA founder and CEO Jensen Huang described the partnership as one spanning nearly three decades. "TSMC is bringing NVIDIA AI and accelerated computing into the fab itself, tackling some of the world's most complex design and manufacturing challenges with simulation, optimization and AI to improve speed, efficiency and yield for the next generation of chips," Huang said.

TSMC chairman and CEO C.C. Wei echoed the sentiment, framing the collaboration as central to the company's manufacturing ambitions. "By using NVIDIA accelerated computing and AI across fab operations optimization, lithography, process control, and inspection, TSMC is strengthening our technology leadership and manufacturing excellence to support our customers' future products and success," Wei said.

The announcement reflects the growing computational demands of advanced semiconductor nodes. As chips move to smaller geometries, the processes required to bring them from design to high-volume production have become increasingly intensive, requiring massive-scale simulation and real-time optimization across physics modeling, image analysis, and operational logistics.

Accelerating Lithography and Simulation Workloads

At the core of the collaboration is TSMC's adoption of NVIDIA CUDA-X libraries and AI models, which the company is running on NVIDIA GPUs to accelerate workloads that were previously handled by CPU-based systems.

In computational lithography, TSMC is using NVIDIA cuLitho, a GPU-accelerated library designed for the chip mask design printing process. According to NVIDIA, this technology delivers a 20 to 50 percent improvement in cost effectiveness or cycle time compared with CPU-based computational lithography, while maintaining the same cost of ownership.

For transistor, equipment, and process simulation, TSMC is deploying NVIDIA cuEST, a GPU-accelerated electronic structure simulation library. NVIDIA states that cuEST enables 50 times faster chemistry simulations on average for semiconductor material design, a figure that could significantly compress the timeline for evaluating new materials and process chemistries.

Process Control and Fab Scheduling Gains

TSMC is also applying NVIDIA's cuML machine learning library to accelerate large-scale analytics on NVIDIA GPUs for advanced process control.

The library allows TSMC to process hundreds of thousands of process parameters spanning thousands of manufacturing steps, distilling them into precision inputs for machine learning models. NVIDIA says this capability is enabling significant reductions in process variation, a critical factor in improving chip yield at advanced nodes.

On the operational side, TSMC has implemented GPU-accelerated scheduling computation using CUDA running on NVIDIA H200 GPUs. According to NVIDIA, this has led to notable improvements in fab productivity by enhancing TSMC's ability to manage complex constraints, streamlining production paths, and maximizing throughput across its manufacturing operations.

Vision AI Targets Nanometer-Scale Defect Detection

As semiconductor geometries shrink, even microscopic defects can have outsized consequences for chip quality and production yield. TSMC is addressing this challenge using the NVIDIA Metropolis platform and NVIDIA TAO Toolkit to advance automated defect classification through vision AI.

The system has improved TSMC's ability to detect defects at the nanometer scale. Beyond raw detection capability, the approach also reduces the need for repeated labeling and retraining as process conditions, inspection tools, and defect types evolve over time.

This adaptability is particularly relevant in a manufacturing environment where process parameters are continuously refined, and new defect categories can emerge as nodes advance.

FabTwin: Building a Virtual Semiconductor Fab

Perhaps the most forward-looking element of the partnership is TSMC's exploration of NVIDIA Omniverse libraries to construct what the company is calling FabTwin, a virtual fab environment designed to evaluate process tool layouts and related simulation workflows before any physical implementation takes place.

Advanced semiconductor fabs are described by NVIDIA as among the most complex manufacturing environments ever built, requiring precise coordination across tools, materials, robots, workers, and facility infrastructure. FabTwin allows TSMC to test design scenarios digitally, compare complex configurations with greater flexibility, and identify potential constraints earlier in the planning process.

By validating layout decisions and simulation workflows in a virtual environment first, TSMC can make critical planning decisions before committing physical resources or capital. NVIDIA says this virtual-first approach vastly improves planning efficiency and accelerates decision-making cycles.

Scope of the Integration

The breadth of the announced collaboration is notable for the number of distinct manufacturing domains it encompasses. Rather than a single-point technology deployment, TSMC appears to be integrating NVIDIA tools across the full semiconductor manufacturing lifecycle, from the earliest stages of chip mask design and material simulation through real-time process control, defect inspection on the factory floor, and high-level facility planning.

The announcement was made at NVIDIA GTC Taipei, where Huang delivered a keynote address. NVIDIA describes itself as the world leader in AI and accelerated computing and trades on the NASDAQ under the ticker NVDA.

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