Inside a facility that began with 25 employees in 1980, Intel Foundry is now running some of the most advanced semiconductor packaging operations in the United States, using a combination of stacking and interconnect technologies designed to meet the surging computational demands of artificial intelligence workloads.

The Rio Rancho, New Mexico site, home to Intel's Fab 9, has grown to 2,700 employees and 500 suppliers and is now positioned as the leading U.S. location for advanced packaging, according to the company.

The work happening there is reshaping how chips are designed and assembled. Rather than relying on a single large processor, Intel Foundry is constructing what it describes as a "silicon mosaic", packages in which multiple specialized chips, or chiplets, are interconnected and function as one unified system. The facility is already scaling packages to eight times the industry's standard reticle limit, with plans to exceed twelve times that limit by 2028.

From Wafer Manufacturing Pioneer to Advanced Packaging Leader

The transformation of the New Mexico site reflects broader shifts in the semiconductor industry. Katie Prouty, manager of Fab 9, noted that the site was a leader in six-inch wafer manufacturing in the 1980s.

Four decades later, its role has fundamentally changed. "Back in the 1980s, this site was the leader in 6-inch wafer manufacturing. Now, over 40 years later, things have flipped, and this site is the leader in the United States for advanced packaging," Prouty said.

That evolution tracks with changes in what chipmakers need. As artificial intelligence applications impose increasingly heavy processing requirements, single-chip designs face physical and economic constraints.

Advanced packaging, the practice of combining multiple chips into a single high-performance unit, has emerged as the industry's answer to those constraints, and Intel says it has been developing and refining these capabilities for years both domestically and globally.

Prouty also pointed to the business dimension of the facility's work. "Some of the customers are coming to us first for advanced packaging," she said. "When we're successful delivering to those customers, they'll continue to grow their trust and faith in Intel as a foundry."

How Foveros Stacking Brings Chiplets Together

One of the primary technologies operating at Fab 9 is Foveros, Intel Foundry's three-dimensional chip stacking process. Chris Seibert, a principal engineer at the New Mexico facility, described the process using a food analogy that has become standard in explaining it internally.

A silicon interposer, the base layer, is treated like a pizza crust, and the individual chiplets placed on top are the toppings. The chip attach tool brings these elements together in the first step of the process.

From there, the assembled wafer moves to what Seibert described as a literal oven, where the system is baked together. Overhead robots using front-opening unified pods, known as FOUPs, then carry the wafer to another machine where epoxy is applied under and around the chiplets to press everything firmly into place. Finally, water-cooled blades dice the wafers into individual packages with precision.

"The great part about that process is it lets us take a bunch of different chips from different designs or different technology nodes and put them all together onto one wafer," Seibert said.

Beyond raw performance, Foveros delivers practical benefits across a range of devices. By placing power-hungry circuits on more efficient process nodes, the technology helps extend laptop battery life, contributes to thinner device designs, and enables smaller edge computing hardware without sacrificing performance. It also allows more features to be packed into a reduced physical footprint, from industrial environments to consumer electronics.

EMIB: Embedding Silicon Bridges Where They Are Needed

While Foveros handles vertical stacking, a separate Intel Foundry technology called EMIB, Embedded Multi-Die Interconnect Bridge — manages lateral connections between chips sitting side by side on a package.

Rather than covering an entire substrate with an expensive silicon interposer as some other foundries do, EMIB places tiny, high-speed silicon bridges only in the locations where chips need to communicate with each other.

Intel describes this as a data shortcut, a targeted connection that lowers costs while delivering the bandwidth required by AI systems. In a data center configuration, for example, large chips sitting adjacent to one another can be linked through an EMIB bridge embedded directly beneath them, allowing them to exchange data rapidly without the overhead of routing signals across a full interposer.

The approach also gives Intel Foundry the ability to mix and match chiplets from different manufacturers and process nodes on what the company says are the industry's largest substrates. That flexibility is central to how Intel positions its packaging capabilities for AI infrastructure customers building large-scale compute systems.

EMIB-T Adds Power Delivery Through the Bridge

The next step in that technology roadmap is EMIB-T, which Intel says is arriving in 2026. The advancement builds on the existing EMIB architecture by adding channels through the silicon bridge itself to deliver power directly to chips, rather than routing power around the bridge.

According to Intel, this improves both power efficiency and signal routing, capabilities that are increasingly important as packages integrate the latest high-bandwidth memory technologies.

The company framed EMIB-T not just as a performance improvement but as an expansion of design freedom. Intel Foundry claims it is the only foundry capable of combining chiplets from multiple sources on substrates of this scale using this combination of technologies, a distinction it says is central to its value proposition for AI data center customers.

Together, Foveros, EMIB, and the forthcoming EMIB-T represent Intel Foundry's layered strategy for addressing AI's escalating demands — building up, building across, and now delivering power more efficiently through the very bridges that connect chips together.

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