IBM (Technology Company) has announced a major semiconductor breakthrough with the introduction of the world's first sub-1 nanometer chip technology, featuring a transistor architecture operating at the 0.7 nanometer, or 7 angstrom, node.

The announcement, made from Yorktown Heights, New York, marks what the company describes as a landmark moment for an industry confronting the physical limits of traditional chip scaling.

A New Threshold in Transistor Density

The sub-1 nm chip packs nearly 100 billion transistors onto a surface the size of a fingernail, representing nearly twice the density of IBM's 2 nm chip, which the company unveiled in 2021.

According to published technical results, the new chip is projected to offer up to 50 percent more performance or 70 percent greater energy efficiency compared to IBM's 2 nm node chips.

Jay Gambetta, Director of IBM Research and IBM Fellow, said the company is not simply shrinking existing transistor designs but fundamentally rethinking chip construction.

"With our new nanostack architecture, we're not just making smaller transistors, we're reinventing how chips are built to deliver dramatically more power and energy efficiency," Gambetta said. "This industry-first innovation continues IBM's legacy of leading in next-generation technologies and sets the foundation for the next era of computing."

IBM said the technology is intended to accelerate computing for applications spanning generative AI, cloud infrastructure, and next-generation electronic devices.

What the Nanostack Architecture Involves

Central to the breakthrough is a new transistor design IBM calls nanostack, which the company describes as the industry's first known three-dimensional, nanosheet-based transistor architecture.

IBM noted that nanosheet technology itself, the current industry-leading architecture, was originally invented by IBM, and that nanostack represents a significant advance beyond it.

The nanostack design vertically stacks and staggers transistors using what IBM describes as 3D sequential integration. This approach allows more transistors to be placed on a chip while also enabling the use of different material combinations within each stacked layer. According to IBM, this makes it possible to optimize the performance and power efficiency of each transistor independently.

IBM said the nanostack architecture was experimentally validated through ultra-thin dielectric bonding in CMOS integration, demonstration of dual-channel engineering capability, and functional CMOS inverter operation with expected switching performance. The company said these results confirm that the nanostack technology can be physically built and supports real computation.

SRAM Scaling and AI Workload Demands

In research presented at VLSI 2026, IBM researchers demonstrated that the nanostack architecture delivers 40 percent scaling in SRAM. IBM said this advancement unlocks the ability for chip designers to create more efficient chips while also meeting the high-bandwidth data demands of advanced AI workloads.

The company described the transition to 0.7 nm, or 7 angstroms, as the beginning of an era of angstrom-level scaling, where chip dimensions approach the size of individual atoms.

IBM noted that while transistor node names now refer to a generation of manufacturing technology rather than an exact physical measurement, the new architecture demonstrates that continued miniaturization remains achievable. IBM said its semiconductor roadmap projects at least a decade of future scaling enabled by the nanostack design.

Research Infrastructure and Industry Partnerships

IBM and its partners conduct semiconductor research at a facility in Albany, New York. That facility is expected to soon house a High Numerical Aperture Extreme Ultraviolet, or High NA EUV, lithography tool developed by ASML, which IBM described as essential for the future of logic scaling. The tool enables ultra-precise circuit printing and supports the creation of smaller, more powerful chips.

IBM said it has been working with partners including Lam Research Corp., Tokyo Electron, and SCREEN Semiconductor Solutions to develop new High NA EUV processes and tools, and that this collaborative work has already yielded working devices.

Quantum Computing and a Path to Production

Alongside its semiconductor announcement, IBM referenced a separate but related initiative. The company recently announced a plan to form Anderon, described as the world's first pure-play quantum foundry.

Anderon will operate as a standalone IBM company and is intended to draw on IBM's quantum computing and semiconductor expertise to help position the United States to manufacture the majority of the world's quantum wafers.

On the commercial timeline for the sub-1 nm chip, IBM said it sees a path to production in as early as the next five years, with nanostack technology expected to see its earliest adoption at the sub-1 nm node.

Decades of Semiconductor Research Behind the Breakthrough

IBM framed the announcement within a longer history of semiconductor leadership that it traces from early chip development in the 1960s through to the first 2 nm node chip. The company said it continues to innovate in silicon, AI hardware, logic, and quantum processors.

Semiconductors, IBM noted, play critical roles across a broad range of sectors, including computing, consumer appliances, communication devices, transportation systems, and critical infrastructure.

The company said more than 4,000 government and corporate entities in critical infrastructure areas, including financial services, telecommunications, and healthcare, rely on IBM.

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