Top 10 Largest Semiconductor Fabs in the World 2026

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Top 10 Largest Semiconductor Fabs in the World 2026

Updated on May 26, 2026, 06:36 PM IST

The global semiconductor industry surpassed USD 320 billion in record foundry revenue in 2025. More than 97 new high-volume fabs broke ground between 2023 and 2025 alone, representing trillions of dollars in committed capital from governments and chipmakers.

 

At the center of this expansion sit the top five largest semiconductor fabs in the world, including Samsung's Pyeongtaek campus, SK Hynix Korea Fabs, TSMC Taiwan Network (all fabs), TSMC Fab 18 (Tainan gigafab), and SMIC Shanghai.

 

This article profiles the ten largest semiconductor fabrication plants and campuses in the world, ranked by production capacity. For each facility, we cover its owner, location, process nodes, lithography technology, key customers, investment scale, and the latest operational news. 

List of Top 10 Largest Semiconductor Fabs in the World 2026

Fab / Campus

Owner

Location

Capacity (WSPM)

Type

Status

Samsung Pyeongtaek Campus (P1-P4)

Samsung Electronics

Pyeongtaek, South Korea

~650,000 WPM

total DRAM + NAND + logic

Memory + Logic

Operational

SK Hynix Korea Fabs (M10-M16 + M15X)

SK Hynix

Icheon + Cheongju, South Korea

~600,000 WPM

ramping H2 2026 with M15X online

Memory (DRAM/HBM)

Ramping

TSMC Taiwan Network (all fabs)

TSMC

Hsinchu / Taichung / Tainan, Taiwan

~1.4M+ WPM

12-inch equiv. across all Taiwan fabs

Logic Foundry

Operational

TSMC Fab 18 (Tainan gigafab)

TSMC

Tainan, Taiwan

~270,000 WPM

3nm/5nm; 272K WSPM by end-2025

Logic Foundry

Operational

SMIC Shanghai (Zhangjiang + Lingang)

SMIC

Shanghai, China

~200,000-250,000 WPM

est.; 14nm-28nm; legacy & mid-range nodes

Logic Foundry

Operational

TSMC Fab 15 (Taichung)

TSMC

Taichung, Taiwan

~100,000 WPM

28nm-40nm; 300mm gigafab

Logic Foundry

Operational

Intel Ocotillo (Fab 42 + Fab 52)

Intel

Chandler, Arizona, USA

~60,000-80,000 WPM

Fab 52 ~40K WSPM at full ramp (18A); Fab 42 in parallel

Logic (IDM)

Ramping

GlobalFoundries Dresden (Fab 1)

GlobalFoundries

Dresden, Germany

~50,000 WPM

22nm/12nm FDX; Europe's largest fab

Logic Foundry

Operational

TSMC Fab 21 (Phoenix, Phase 1)

TSMC

Phoenix, Arizona, USA

~20,000-30,000 WPM

N4/N5; Phase 1 ramping to 30K; Phase 2 (N3) in construction

Logic Foundry

Ramping

TSMC Kumamoto JASM (Phase 1)

TSMC / Sony / Denso

Kumamoto, Japan

~12,000-20,000 WPM

22nm/28nm; Phase 2 (6nm) under construction

Logic Foundry

Operational

Samsung Pyeongtaek Campus (P1-P4)

Samsung Pyeongtaek Campus (P1-P4)

 

Fab Name

Samsung Pyeongtaek Campus

Location

Pyeongtaek, Gyeonggi Province, South Korea

Owner

Samsung Electronics

Year Established

2015 (First fab started operations in 2017)

Wafer Size

300mm (12-inch)

Process Nodes

3nm, 4nm, 5nm, 7nm, 14nm, DRAM

Type of Fab

IDM (Integrated Design Manufacturers)

Investment Cost

Subscribe to the Global Semiconductor Fab Database

Key Clients

Qualcomm, NVIDIA, IBM, Baidu

Lithography

EUV & DUV Lithography

 

The Samsung Pyeongtaek semiconductor fabrication plant is the world's largest semiconductor production complex by physical footprint, spanning approximately 2.89 million square meters, equivalent to 400 football fields. The campus currently houses four active fabrication lines (P1-P4) producing DRAM, NAND flash, and advanced foundry logic, with a fifth (P5) under accelerated construction.

 

  • P1 (2015-2017): Produces 4th-generation V-NAND (64-layer). Broke ground as the largest single fab in the industry at the time.

  • P2 (2018-2020): 128,999 m² gross area; manufactures 3rd-generation 10nm mobile DRAM (EUV process) and V-NAND.

  • P3 (2022): USD 22 Billion investment; full EUV capability; NAND flash and foundry logic down to 5nm.

  • P4 (~USD 36 Billion): Accelerated to maximum production six months early using temporary-use permits to begin cleanroom installation before building completion. Positioned as a core HBM4 production base for NVIDIA Vera Rubin AI accelerators.

  • P5 (under construction, target 2028): Largest and tallest plant on the campus - six cleanrooms across three floors (vs. four cleanrooms on two floors for earlier fabs). Estimated investment USD 23-66 Billion.

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SK Hynix Korea Fabs (M10-M16 + M15X)

Fab name

SK Hynix M-series (M10-M16) + M15X

Location

Icheon (M10-M14, M16) + Cheongju (M15, M15X), South Korea

Owner

SK Hynix (SK Group)

Year established

M15X: construction Oct 2022; operations Feb 2026 (4 months early)

Wafer size

300mm (12-inch)

Process nodes

1b DRAM, 1c DRAM, HBM3E, HBM4, LPDDR5, DDR5

Type of fab

IDM (Memory)

Investment

M15X: ~USD 14 Billion (20 trillion won); Yongin cluster: ~USD 84 Billion Phase 1

Key clients

NVIDIA (Blackwell, Rubin GPUs), Google, Amazon, Microsoft, Apple

Lithography

EUV + DUV

Capacity (WPM)

~600,000 WPM (ramping H2 2026 with M15X); M15X target 55-60K WPM by Q4 2026

 

SK Hynix is the world's largest HBM (High-Bandwidth Memory) supplier, holding approximately 53% of the HBM market as of Q3 2025. Its Korea network of fabs produces DRAM, HBM3E, and HBM4 for AI accelerators including NVIDIA's Blackwell and Rubin platforms.

 

M15X (Cheongju) - SK Hynix's first new fab since its 10th anniversary. Construction began in October 2022 and finished two months ahead of schedule. Originally planned to begin wafer insertion in June 2026, the company started commercial production of 1b DRAM (HBM4 core die) in February 2026 (four months early) to meet NVIDIA demand. Initial capacity ~10,000 WPM, ramping to 55,000-60,000 WPM by Q4 2026. The fab was launched in May 2026, as reported.

 

Total DRAM capacity (with M15X) is ~550,000-600,000 WPM, ramping toward parity with Samsung's 650,000 WPM by H2 2026. Yongin Semiconductor Cluster is an upcoming four-fab National Industrial Complex with an estimated investment of ~600 trillion won (~USD 430 billion). Phase 1 fab targets completion in May 2027. When fully ramped, it will add ~350,000 WPM, lifting total capacity to ~900,000 WPM.

TSMC Taiwan Network (all fabs)

TSMC Taiwan Network (all fabs)

 

Fab name

TSMC Taiwan Fabs (Fab 12, 14, 15, 18, 20, 22 + 8" fabs)

Location

Hsinchu, Taichung, Tainan, Kaohsiung - Taiwan

Owner

TSMC (Taiwan Semiconductor Manufacturing Co.)

Year established

Fabs from 1990s; Fab 18: 2018; Fab 20: 2022

Wafer size

300mm (12-inch) + 200mm (8-inch) + 150mm (6-inch)

Process nodes

2nm, 3nm, 5nm, 7nm, 16nm, 28nm, 40nm+

Type of fab

Pure-play foundry

Investment

Hundreds of billions cumulative; ~ USD 38-40 Billion annual capex

Key clients

Apple, NVIDIA, AMD, Qualcomm, MediaTek, Intel, Broadcom, Google, Amazon

Lithography

High-NA EUV (2nm+), Low-NA EUV, DUV immersion

Capacity (WPM)

1.4M + WPM (12" equivalent); 17M+ 12" equiv. wafers/year (2025)

 

TSMC is the world's largest pure-play foundry with 65% of the global foundry market share and approximately 92% of the sub-5nm market by revenue. Its annual capacity exceeded 17 million 12-inch equivalent wafers in 2025, the company's biggest year ever. The network includes six 12-inch GigaFab® facilities, four 8-inch fabs, and one 6-inch fab.

 

Key Taiwan fabs include Fab 12 (Hsinchu, 0.15μm-0.10μm), Fab 14 (Hsinchu, 20nm-5nm), Fab 15 (Taichung, 28nm-40nm, ~100,000 WPM), Fab 18 (Tainan, 3nm-5nm, see separate entry), and Fab 20 (Tainan, 2nm).

 

2nm ramp: TSMC entered 2nm (N2) mass production in late 2025. Monthly capacity is expected to reach nearly 100,000 WPM by the end of 2026, with Apple as the launch customer and NVIDIA's next-gen "Rubin" platform expected in 2026. 3nm capacity is simultaneously expanding toward 180,000-200,000 WPM by end-2026.

 

At its Q1 2026 earnings call, Chairman C.C. Wei reaffirmed Taiwan as the primary base for leading-edge production. TSMC's total advanced capacity remains booked through 2028, with 2nm wafer pricing expected to exceed USD 30,000/wafer. TSMC is planning annual price hikes of 3-5% for sub-5nm nodes through at least 2029. Fab 18B's P7 and P8 phases are currently being equipped, with all eight phases expected to deliver ~200,000 WPM of 3nm capacity.

TSMC Fab 18 (Tainan gigafab)

Fab name

TSMC Fab 18 (Fab 18A: 5nm; Fab 18B: 3nm)

Location

Southern Taiwan Science Park, Tainan, Taiwan

Owner

TSMC

Year established

Groundbreaking Jan 26, 2018; Phase 1 production 2020

Wafer size

300mm (12-inch)

Process nodes

3nm (N3/N3E)4nm (N4/N4P)5nm (N5/N5P)

Type of fab

Pure-play foundry

Investment

~NT$500B (~$17B construction); total 5nm/3nm program ~$24B

Key clients

Apple (A-series, M-series), NVIDIA (H100/H200/Blackwell), AMD (EPYC/Instinct), Qualcomm, MediaTek

Lithography

EUV (Low-NA) + DUV immersion

Capacity (WPM)

~270,000 WPM (Fab 18A + 18B combined); 3nm targeting 180K+ WPM by end-2026

 

TSMC's fourth and largest 12-inch GigaFab® in Taiwan, and the single largest advanced-logic fab in the world. Built on 42 hectares with a floor area of 950,000 m² and a cleanroom area of 160,000 m² (equivalent to 25 football fields). Fab 18 is purpose-built for TSMC's most advanced nodes and powers chips for Apple, NVIDIA, AMD, and Qualcomm.

  • Phase 1 (5nm): Production began Q4 2020

  • Phase 2 (5nm): Production began in 2020

  • Phase 3 (5nm/4nm): Production began in 2021

  • Fab 18B (3nm): Eight phases (P1-P8); 25,000 WPM per phase. 3nm capacity surpassed 150,000 WPM by end-2025, ahead of schedule. Phases P7 and P8 are currently being ramped; full 8-phase capacity will deliver ~200,000 WPM.

SMIC Shanghai (Zhangjiang + Lingang)

Fab name

SMIC Shanghai Fabs (Zhangjiang + Lingang campuses)

Location

Zhangjiang Hi-Tech Park + Lingang, Shanghai, China

Owner

SMIC (Semiconductor Manufacturing International Corp.)

Year established

2000 (company founded; Zhangjiang Fab 1 operational)

Wafer size

300mm (12-inch) + 200mm (8-inch)

Process nodes

7nm (DUV MPT), 14nm, 28nm, 40nm, 65nm+

Type of fab

Pure-play foundry

Investment

~USD 6–9 BIllion (Zhangjiang campus); 4 new fabs >USD 20 Billion combined investment

Key clients

Huawei (HiSilicon), Xiaomi, UNISOC, domestic Chinese fabless firms

Lithography

DUV immersion (multi-patterning) - no EUV access (US export controls)

Capacity (WPM)

~200,000–250,000 WPM (est.); Shanghai + Tianjin new fabs nearing completion (28nm, 2025–26)

 

SMIC is China's largest and most advanced semiconductor foundry and the anchor of China's strategy for domestic semiconductor self-sufficiency. It is the fourth-largest foundry globally by revenue. The Shanghai campus includes multiple fab lines operating nodes from 0.35μm down to 7nm (achieved via multi-patterning DUV, as EUV is inaccessible under US export controls).

 

SMIC's 7nm DUV multi-patterning capability - confirmed in chips found inside Huawei's Mate 60 Pro (2023) - represented a major milestone, demonstrating that China could achieve near-leading-edge production without ASML's EUV machines. 

 

SMIC cannot currently reach 5nm or below, limiting competitiveness against TSMC and Samsung for AI chip orders. Its strength lies in mature nodes (28nm, 40nm, 65nm), which are critical for automotive, IoT, consumer electronics, and industrial chips.

 

SMIC's Shanghai (USD 8.87 billion) and Tianjin (USD 7.5 billion) fabs targeting 28nm are nearing completion, with operations expected to start in 2025-2026. Huawei and SMIC are reportedly aiming for the 5nm node using aggressive multi-patterning DUV techniques, though yield challenges remain. YMTC (memory peer) announced a third memory fab in China.

TSMC Fab 15 (Taichung)

Fab name

TSMC Fab 15A (28nm/40nm) + Fab 15B (3nm supplement)

Location

Taiwan Science Park, Taichung, Taiwan

Owner

TSMC

Year established

Phase 1 completed June 2011; volume production Q1 2012

Wafer size

300mm (12-inch)

Process nodes

28nm, 40nm, 3nm (Fab 15B)

Type of fab

Pure-play foundry

Investment

~NT USD 300 Billion (~USD 9 Billion)

Key clients

Qualcomm, MediaTek, NXP (automotive), Texas Instruments, Broadcom, Apple

Lithography

DUV immersion (28nm/40nm); EUV (Fab 15B 3nm supplement)

Capacity (WPM)

~100,000 WPM (Fab 15A); Fab 15B at full load 4,500–5,000 wafers/day (3nm)

 

TSMC's 28nm-40nm workhorse fab and one of its largest mature-node production facilities. Built on 18.4 hectares with a building area of 430,000 m² and a cleanroom area equal to 14 football pitches. Fab 15A produces 28nm and 40nm chips at ~100,000 12-inch WPM, and Fab 15B was converted to supplement 3nm production and has been ramped to full load.

 

Fab 15B is now operating at full load with a stable 4,500-5,000 wafer daily output at 3nm, supplementing Fab 18B's 3nm capacity. The mature-node segment at Fab 15 continues to serve automotive and IoT customers, where demand for 28nm nodes remains strong and growing.

Intel Ocotillo (Fab 42 + Fab 52)

Intel Ocotillo (Fab 42 + Fab 52)

 

Fab name

Intel Ocotillo Campus (Fab 42; Fab 52, Fab 62 u/c)

Location

Chandler (Ocotillo), Arizona, USA

Owner

Intel Corporation

Year established

Site: 1979; Fab 42: 2011-2017; Fab 52: construction 2021, operational 2025–26

Wafer size

300mm (12-inch)

Process nodes

Intel 18A (1.8nm), Intel 3, Intel 4, Intel 7, Intel 14A (Fab 62, future)

Type of fab

IDM + external foundry (Intel Foundry Services)

Investment

USD 50 B+ cumulative (site); USD 32B for Fab 52 + Fab 62; CHIPS Act grant: USD 7.86B

Key clients

Internal (Intel CPUs/GPUs); external: Microsoft, AWS (18A-P); Tesla/SpaceX/xAI (Terafab pact, Apr 2026)

Lithography

Low-NA EUV (ASML NXE:3800E + NXE:3600D); 15+ EUV scanners planned across campus; High-NA EUV for Fab 62

Capacity (WPM)

Fab 52: ~40,000 WPM at full ramp (18A); Fab 42 parallel; combined ~60,000-80,000 WPM

 

Intel's primary advanced manufacturing site in the US is the most advanced logic fab in the Americas. The Ocotillo campus, one of the largest semiconductor fabs in the US, spans approximately one square mile (700 acres) and now houses three high-volume fabs (Fab 42; Fab 52, and Fab 62 in construction). Intel began manufacturing in Arizona in 1979 and has since invested over USD 50 billion at the site.

 

Fab 52 (18A / 1.8nm-class): Construction started late 2021 and is fully operational as of late 2025. Uses GAA (Gate-All-Around) RibbonFET transistors and PowerVia backside power delivery. Production capacity at full ramp is ~40,000 WSPM (10,000 wafer starts/week). 

 

Equipped with at least 4 ASML NXE Low-NA EUV scanners, with a total planned 15+ EUV machines across the Ocotillo campus. Handles roughly twice the wafer volume of TSMC's Fab 21 Phase 1 at a more advanced node. Fab 62 (14A) - construction began in 2024 and expected completion ~2027-2028. It will use next-generation Intel processes for AI and HPC chips.

GlobalFoundries Dresden (Fab 1)

Fab name

GlobalFoundries Fab 1 (formerly AMD Fab 30/36)

Location

Dresden, Saxony, Germany

Owner

GlobalFoundries (Mubadala Investment Company)

Year established

1994 (AMD); became GlobalFoundries in 2009

Wafer size

300mm (12-inch)

Process nodes

22nm FDX12nm FDX28nm55nm+

Type of fab

Pure-play foundry

Investment

~USD 10B+ cumulative; EUR 1.1B current expansion (EUR 495M German Chips Act)

Key clients

Bosch, NXP, Infineon, STMicroelectronics, Qualcomm, RF/automotive OEMs, US DoD (Trusted Foundry)

Lithography

DUV immersion + DUV dry

Capacity (WPM)

~50,000 WPM (300mm)

 

Europe's largest semiconductor fab and the continent's most important foundry facility. Originally built by AMD as part of a joint venture with Fujitsu, it was spun out into GlobalFoundries in 2009. The Dresden Fab 1 specializes in 22nm FD-SOI (22FDX) and 12nm FDX process technologies, mature but highly efficient nodes suited to RF chips, automotive, IoT, and low-power applications.

 

The fab employs thousands of workers and is a cornerstone of Germany's semiconductor ecosystem. Its 22FDX process is uniquely competitive for automotive radar, RF front-ends, and microcontrollers. 

 

The German government confirmed EUR 495M in Chips Act support for GF's EUR 1.1B Dresden expansion plan. GF also announced in June 2025 a broader USD 16B US investment across its New York and Vermont fabs. A planned joint fab in Crolles, France, with STMicro has stalled.

TSMC Fab 21 (Phoenix, Phase 1)

Fab name

TSMC Fab 21 (Phase 1: N4/N5; Phase 2: N3; Phase 3: N2/A16)

Location

North Phoenix, Arizona, USA

Owner

TSMC (CHIPS Act: USD 6.6 Billion grant + USD 5 Billion loans)

Year established

Construction began April 2021; Phase 1 production Q4 2024

Wafer size

300mm (12-inch)

Process nodes

N4/N4P (Phase 1), N5 (Phase 1), N3 (Phase 2, 2027), N2/A16 (Phase 3, ~2030)

Type of fab

Pure-play foundry

Investment

USD 165 B (6-fab campus); May 2026: additional USD 20 B board-approved; long-term up to USD 465 B

Key clients

Apple (#1, 100M+ chips in 2026), NVIDIA (Blackwell), AMD, Broadcom

Lithography

EUV (Low-NA) + DUV immersion

Capacity (WPM)

Phase 1: ~20,000–30,000 WPM (ramping); Phase 2 equipment install begins Q3 2026

 

TSMC's flagship US fab is the only sub-5nm manufacturing facility on American soil. Phase 1 (Fab 21 P1) produces 4nm/5nm chips and came online in late 2024, initially at 10,000 WPM and ramping toward 30,000 WPM. Apple is the largest customer, receiving "tens of millions" of Apple Silicon chips in 2025 and over 100 million chips planned for 2026. NVIDIA is also using Fab 21 for some Blackwell AI accelerator production.

 

The facility employs ~3,000 engineers and uses approximately 700 FOUPs (Front-Opening Unified Pods) on automated overhead transport systems, with EUV lithography as its cornerstone. An industrial water reclamation system recycles up to 90% of the water used.

 

Phase 2 (3nm): Construction completed April 2026. Equipment installation to begin Q3 2026 (accelerated from original 2028 target), with volume production targeted for 2027. This is years ahead of the original plans.

 

Phase 3 (2nm/A16): Broke ground in April 2025 and production targeted by the end of the decade.

TSMC Kumamoto JASM (Phase 1)

Fab name

JASM (Japan Advanced Semiconductor Manufacturing) - TSMC Fab 23

Location

Kikuyo-machi, Kumamoto Prefecture, Japan

Owner

TSMC (86.5%), Sony (6%), Denso (6%), Toyota (1.5%)

Year established

Construction 2022; Phase 1 opened February 2024

Wafer size

300mm (12-inch)

Process nodes

22nm (Phase 1), 28nm (Phase 1), 3nm (Phase 2, upgraded from 6nm)

Type of fab

Pure-play foundry (joint venture)

Investment

~USD 8.6B (Phase 1 + 2); Japanese govt subsidy ~Yen 476B (~USD 3.2B) for Phase 1

Key clients

Sony (image sensors), Denso/Toyota (automotive), Renesas, NXP, Texas Instruments

Lithography

DUV immersion (Phase 1); EUV (Phase 2, 3nm)

Capacity (WPM)

~12,000-20,000 WPM (Phase 1); Phase 2 (3nm) adds further capacity from 2027-28

 

Japan's most advanced semiconductor fab and TSMC's first overseas GigaFab. Phase 1 (JASM Fab 1) produces 22nm/28nm chips with a focus on automotive, IoT, and industrial applications, nodes in high demand among Japanese OEMs like Toyota and Sony. It opened on schedule in February 2024, marking a milestone in Japan's semiconductor revival strategy.

 

Phase 2 (JASM Fab 2, 6nm/7nm): The plant is under construction with expected production ~2027. The Japanese government is providing additional subsidies. Recent reports indicate TSMC is upgrading Phase 2 targets from 6nm to 3nm to serve automotive and AI customers, a significant elevation from original plans.

Top 5 Upcoming Semiconductor Fabs - May 2026

Fab / Campus

Owner

Location

Type

Status

SK Hynix Yongin Cluster - Fab 1 of 4

SK Hynix (SK Group)

Yongin, South Korea

Memory - DRAM / HBM4 / HBM4E

Under construction

Micron New York Megafab - Clay, Fab 1 of 8

Micron Technology

Clay (Syracuse), New York, USA

Memory - DRAM / HBM

Under construction

Samsung Pyeongtaek P5

Samsung Electronics

Pyeongtaek, South Korea

Memory - HBM4 / 1c DRAM

Under construction

TSMC Fab 21 Phase 2 - Arizona

TSMC

North Phoenix, Arizona, USA

Logic Foundry - 3nm (N3)

Equipment installation starts in Q3 2026

Rapidus IIM - Chitose, Hokkaido

Rapidus

Chitose, Hokkaido, Japan

Logic Foundry - 2nm GAA

Pilot production underway

Conclusion

The ten facilities profiled here represent the backbone of global semiconductor supply in 2026.

SK Hynix's Yongin cluster, Micron's New York megafab, Samsung's P5, and Japan's Rapidus will collectively add over a million new wafer starts per month by the early 2030s, capacity that did not exist five years ago. 

 

Fab construction costs continue to rise, with a single leading-edge facility now routinely exceeding USD 20 billion, making national governments as important as private capital in deciding where chips get made. The geopolitical map of semiconductor manufacturing is being redrawn in real time, and the fabs covered in this article are where that future is being built with one wafer at a time.

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