TSMC (Taiwan Semiconductor Manufacturing Company) has introduced its A13 process technology at the company's 2026 North America Technology Symposium (Event) in Santa Clara, California, presenting the new node as a direct shrink of its A14 platform and a step forward in density and energy efficiency for artificial intelligence, high-performance computing, and mobile applications.

A13 as a Direct Shrink of A14

The A13 process delivers a 6% area savings compared to A14, the node TSMC announced in 2025. TSMC described the design rules as fully backward compatible with A14, meaning customers can migrate their existing designs to the new nanosheet transistor technology without starting from scratch.

The company said A13 also delivers increased power efficiency and performance gains through design-technology co-optimization. Production is scheduled to begin in 2029, one year after A14 enters production.

TSMC Chairman and CEO Dr. C.C. Wei said that customers come to the company for a reliable stream of new silicon technologies engineered to be ready for high-volume production when their designs demand them. He described TSMC's advanced process technologies as leading the industry in density, performance, and power efficiency.

The 2026 North America Technology Symposium opened the company's annual global event series, which will continue in other regions in the coming months. The theme of this year's symposiums is "Expanding AI with Leadership Silicon."

A12 and N2U Join the Advanced Logic Roadmap

Beyond A13, TSMC also previewed A12, described as a platform enhancement of A14 that incorporates Super Power Rail technology to provide backside power delivery for AI and HPC applications. A12 is also scheduled to enter production in 2029.

The company additionally introduced N2U, a further development of its 2nm platform. N2U uses design-technology co-optimization to achieve speed gains of 3 to 4 percent or power reduction of 8 to 10 percent, along with a 1.02 to 1.03 times logic density improvement over N2P.

TSMC characterized N2U as a balanced option for AI, HPC, and mobile applications, leveraging the process maturity and yield performance already established within the 2nm technology platform. N2U is scheduled for production in 2028.

CoWoS Packaging Expands Toward 14-Reticle Scale and Beyond

On the packaging side, TSMC announced significant expansions to its Chip on Wafer on Substrate, or CoWoS, technology. The company is currently producing 5.5-reticle size CoWoS and is planning for larger configurations.

A 14-reticle size CoWoS capable of integrating approximately 10 large compute dies and 20 HBM stacks is slated for production in 2028, with an expansion beyond 14 reticles planned for 2029. These offerings are intended to give customers more options for AI compute scaling.

Alongside CoWoS, TSMC also referenced its 40-reticle size SoW-X System-on-Wafer technology, which is expected in 2029.

The company announced that its TSMC-SoIC 3D chip stacking technology will be available on its most advanced platform, with A14-to-A14 SoIC set for production in 2029.

That configuration will provide 1.8 times higher die-to-die input/output density compared with N2-on-N2 SoIC, supporting higher bandwidth data transfer between stacked chips.

Co-Packaged Optics Milestone With COUPE on Substrate

TSMC's Compact Universal Photonic Engine, known as TSMC-COUPE, is set to reach a production milestone in 2026 with a co-packaged optics solution using COUPE on substrate.

By integrating the optical engine directly inside the package, TSMC said it achieves two times the power efficiency and ten times the latency reduction compared with a pluggable version mounted on a circuit board.

The technology is featured in a 200 gigabits-per-second micro-ring modulator, described by TSMC as a compact and energy-efficient solution for moving data between racks in data centers.

N2A Brings Nanosheet Transistors to Automotive Applications

TSMC used the symposium to address the automotive and robotics markets, announcing N2A as the first automotive-grade process technology built on nanosheet transistors. The company said N2A provides a 15 to 20 percent speed gain at the same power compared with N3A and is scheduled to complete AEC-Q100 qualification in 2028.

To allow customers an earlier design start ahead of full N2A qualification, TSMC is making what it calls Auto-Use design kits available within its existing N2P process design kit. This allows customers to factor in automotive usage conditions during the design phase before the N2A process is fully certified.

The company also noted that its N3A automotive process is entering production in 2026. Through an N3 Auto Early program, customers were able to begin designs in 2023, and TSMC said more than 10 products are currently planned on N3A technology for automotive use.

N16HV Targets Display Driver Market

In specialty technology, TSMC announced N16HV, which it described as the first high-voltage technology brought into the FinFET era. Targeted at display driver applications, the process is entering production in 2026 and is aimed at increasing gate density for smartphone display driver chips, according to the source material provided.

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